Conventionally, as a substrate for a device, an SOI wafer wherein a silicon active layer (an SOI layer) is formed on a support substrate has been widely utilized. As a method for producing such an SOI wafer, for example, it is known that a so-called bonding method in which two silicon wafers are bonded together via an oxide film.
In ion implantation delamination method which is one of bonding methods, an oxide film (which is also referred to as buried oxide film or interlevel dielectric oxide film) is formed as insulating layer on a surface of a silicon wafer (a bond wafer) to become a silicon active layer or a silicon wafer (a base wafer) to be a support substrate, and an ion-implanted layer (a micro bubble layer) is formed inside the bond wafer by implanting ions such as hydrogen ion from one side surface of the bond wafer. Further, after the surface of the ion-implanted side of the bond wafer is bonded to the base wafer via the oxide film, delamination is performed at the ion-implanted layer by heat treatment. Thereby, an SOI wafer in which a thin silicon active layer is formed on the base wafer via the oxide film can be obtained. Further, after the delimitation, there are also some cases that a heat treatment (a bonding heat treatment) for improving bonding strength between the silicon active layer and the base wafer, cleaning with hydrofluoric acid for removing an oxide film on the surface, or the like is performed.
A silicon single crystal grown by Czochralski method (CZ method) can be generally used as a silicon wafer for producing an SOI wafer as described above. However, in recent years, the demand for thinning the silicon active layer and the buried oxide film increases, and the demand for quality of a silicon wafer applicable to this has also become strict.
Especially, it has been proposed that silicon single crystal with low defect density is grown and a silicon wafer with high quality obtained from the crystal is used as a bond wafer to become the silicon active layer.
Hereafter relations between pulling rate when growing silicon single crystal by Czochralski method and defect of the silicon single crystal to be grown will be explained.
It is known that in the case of changing a growth rate V from high speed to low speed in the direction of a crystal growth axis in a CZ pulling apparatus with a usual furnace structure (hot zone: HZ) inducing a large temperature gradient G at the vicinity of a solid-liquid interface in a crystal, a defect distribution diagram as shown in FIG. 9 can be obtained.
In FIG. 9, V region is a region that contains a large amount of vacancies, i.e., depressions, pits, or the like caused by lack of silicon atoms, and I region is a region that contains a large amount of dislocations or clusters of excess silicon atoms caused by existence of interstitial silicon that is excess silicon atoms. It has also been confirmed that there exists a neutral (hereinafter occasionally abbreviated as N) region that contains no (or little) lack or excess of the atom between V region and I region, and defects called OSF (Oxidation Induced Stacking Fault) are distributed in a ring shape (hereinafter occasionally referred to as OSF ring) near a boundary of V region when observed in the cross section perpendicular to a crystal growth axis.
When the growth rate is relatively high, there exist grown-in defects such as FPD, LSTD and COP, which are considered due to voids consisting of agglomerated vacancy-type point defects, at a high density over the entire radial direction of the crystal, and a region containing these defects becomes V region. Further, along with lowering of the growth rate, the OSF ring is generated from the periphery of the crystal, and N region is generated outside the ring (at lower speed side). When the growth rate is much further lowered, the OSF ring shrinks to the center of the wafer and disappears, so that the entire plane becomes N region. When the growth rate is further lowered, there exist at a low density, L/D (Large Dislocation: an abbreviation for interstitial dislocation loop, such as LSEPD, LFPD and the like) defects (huge dislocation clusters) which are considered due to dislocation loops consisting of agglomerated interstitial silicon, and the region where these defects exist becomes I region (occasionally referred to as L/D region).
N region located between the V region and the I region and outside the OSF ring becomes a region containing no FPD, LSTD and COP to be generated due to voids as well as no LSEPD and LFPD to be generated due to interstitial silicon. In addition, it has been recently found that by further classifying N region, as shown in FIG. 9, there exist Nv region (the region where a lot of vacancies exist) adjacent to the outside of OSF ring and Ni region (the region where a lot of interstitial silicon exist) adjacent to I region, and that when performing thermal oxidation treatment, there exists a large amount of oxygen precipitation in Nv region and little oxygen precipitation in Ni region.
Although such an N region conventionally existed only in a part of a plane of wafer, a crystal having N region over the entire radial plane (the entire surface of wafer), as shown in FIG. 9, has also been able to be manufactured by controlling V/G that is a ratio of a pulling rate (V) to an axial temperature gradient (G) at a solid-liquid interface in a crystal.
And so, in the manufacture of an SOI wafer, there has been proposed a method in which a silicon single crystal wafer having N region over the entire surface is used as a bond wafer. For example, there has been proposed an SOI wafer wherein a silicon single crystal is pulled by controlling a ratio of the pulling rate V to the axial temperature gradient G at a solid-liquid interface of the crystal (V/G) within a predetermined range when it is pulled by Czochralski method, and the silicon wafer in N region is used as a bond wafer (for example, see Japanese Patent Laid-open (Kokai) No. 2001-146498 (on pages 5-8) and Japanese Patent Laid-open (Kokai) No. 2001-44398 (on pages 2-4, in FIG. 1)).
On the other hand, a base wafer is essentially necessary for supporting an SOI layer via an insulator film, and device is not fabricated directly on the surface of the base wafer. Therefore, there has also been proposed that a dummy-grade silicon wafer of which resistivity and the like do not meet product standards is used as a base wafer (see Japanese Patent Laid-open (Kokai) No. 11-40786).
In general, in view of improving quality and productivity and so on, a silicon single crystal including V region or further partially including OSF region or Nv region is grown with pulling rate at high speed as shown in FIG. 9, and a silicon wafer processed to have mirror surface from such a silicon single crystal grown at high speed has been widely used as a base wafer.
Vacancy defects such as COP consisting of agglomerated vacancies are formed with high density on the surface and in the bulk of the silicon wafer obtained from silicon single crystal grown at high speed as described above, and there exist many micro pit defects having the size of 50 nm or more on the surface of the silicon wafer. And when an SOI wafer is produced by using such a silicon wafer having many micro pit defects as a base wafer, especially in the case that a thinner buried oxide film is formed as recently demanded, there arises a problem that high insulating property is not retained and electrical reliability is degraded.